WEBVTT 1 00:00:00.160 --> 00:00:03.600 Inside the computer or the phone you're using right now. 2 00:00:04.120 --> 00:00:07.839 There are literally billions of microscopic water faucets. 3 00:00:07.919 --> 00:00:09.560 Yeah, billions of them. 4 00:00:09.480 --> 00:00:12.880 Right, And because we have spent decades engineering the pipes 5 00:00:12.880 --> 00:00:15.640 to be narrower and narrower, I mean down to just 6 00:00:15.759 --> 00:00:19.199 a few atoms wide, the water is actually starting to 7 00:00:19.280 --> 00:00:24.079 physically leak through the closed valves. We're basically hitting a 8 00:00:24.079 --> 00:00:25.760 hard limit on the laws of physics. 9 00:00:25.760 --> 00:00:29.039 Well, we are talking about electrons obviously, rather than actual water, 10 00:00:29.600 --> 00:00:32.200 but yeah, the physical reality of quantum tunneling and modern 11 00:00:32.240 --> 00:00:35.640 processors is frankly one of the most pressing issues in 12 00:00:35.719 --> 00:00:38.039 hardware design today. It's well, how to think about it 13 00:00:38.079 --> 00:00:40.000 really is. I mean, we abstract so much of this 14 00:00:40.079 --> 00:00:42.880 away when we use technology. It is incredibly easy to 15 00:00:42.920 --> 00:00:46.240 forget that we're ultimately just pushing physical electrons around on 16 00:00:46.240 --> 00:00:46.640 a piece of. 17 00:00:46.640 --> 00:00:49.159 Silicon, which is exactly our mission for you in this 18 00:00:49.240 --> 00:00:53.600 deep dive. We're peeling back that abstraction. Because you write code, 19 00:00:53.640 --> 00:00:56.560 you deploy servers, you run software every day. But today 20 00:00:56.600 --> 00:00:59.640 we're going to demystify the physical reality of how a 21 00:00:59.679 --> 00:01:01.039 computer actually. 22 00:01:00.640 --> 00:01:02.799 Computes right from the ground up exactly. 23 00:01:02.920 --> 00:01:07.599 We're going on a journey from a single microscopic electronic 24 00:01:07.640 --> 00:01:11.120 switch to a fully automated machine that can perform complex math. 25 00:01:11.599 --> 00:01:15.519 And to do this, we're using Douglas Comber's textbook Essentials 26 00:01:15.560 --> 00:01:17.359 of Computer Architecture, which is. 27 00:01:17.359 --> 00:01:19.200 A fantastic resource, by the way. 28 00:01:19.280 --> 00:01:22.959 It really is. It bridges that massive gap between the 29 00:01:23.040 --> 00:01:26.280 high level software you are used to and the incredibly 30 00:01:26.400 --> 00:01:29.319 fast microscopic hardware operating underneath it all. 31 00:01:29.480 --> 00:01:32.439 And you know, I think hardware can seem really impenetrable 32 00:01:32.439 --> 00:01:35.640 from the outside. This sheer scale of it, billions of 33 00:01:35.640 --> 00:01:39.000 components operating in fractions of a nanosecond, it's intimidating. 34 00:01:39.079 --> 00:01:40.439 Oh totally, it feels like magic. 35 00:01:40.560 --> 00:01:44.200 Right, But underneath all that complexity, hardware is actually built 36 00:01:44.239 --> 00:01:48.079 on a surprisingly small set of beautifully simple, repeatable principles. 37 00:01:48.400 --> 00:01:50.040 Okay, so to get to those principles, we have to 38 00:01:50.040 --> 00:01:53.799 start at the foundational layer. Right. Representing information, yes, because 39 00:01:53.840 --> 00:01:57.079 we are dealing with digital computation here, and that relies 40 00:01:57.120 --> 00:02:00.120 on discrete, precise values ones and zero. 41 00:02:00.079 --> 00:02:03.439 Ros exactly as opposed to the continuously varying signals of 42 00:02:03.519 --> 00:02:04.799 older analog computers. 43 00:02:05.120 --> 00:02:09.319 Right. But getting a machine to reliably represent a binary 44 00:02:09.360 --> 00:02:12.840 state took some serious trial in error. I mean we 45 00:02:12.960 --> 00:02:16.599 used mechanical relays originally, which were physically well, just too slow. 46 00:02:16.680 --> 00:02:18.840 Yeah, they literally had physical moving parts, right. 47 00:02:19.000 --> 00:02:21.840 And then we moved to vacuum tubes in the nineteen forties, which. 48 00:02:21.599 --> 00:02:24.439 To be fair, provided a massive leap in switching speed, 49 00:02:24.759 --> 00:02:27.759 but the physical drawbacks were just severe because of the heat. 50 00:02:27.960 --> 00:02:28.240 Heat. 51 00:02:28.400 --> 00:02:31.479 Yes, but also they required a glowing filament, so they 52 00:02:31.560 --> 00:02:35.000 generated immense heat and burned out continuously. I mean a 53 00:02:35.000 --> 00:02:38.360 team running a large tube based machine would have to 54 00:02:38.400 --> 00:02:42.560 halt computation constantly just to replace blown out components, like. 55 00:02:42.560 --> 00:02:45.000 Changing light bulbs in the middle of a math problem basically. 56 00:02:45.120 --> 00:02:48.120 But then came nineteen forty seven and the invention of 57 00:02:48.120 --> 00:02:52.360 the transistor. Yea, yeah, no filament, minimal heat, virtually indestructible. 58 00:02:52.400 --> 00:02:55.680 It changed everything, it really did. But to really grasp 59 00:02:55.919 --> 00:03:01.479 the modern transistor, specifically the moss FETE or metiloxide semiconductive 60 00:03:01.479 --> 00:03:05.120 fuel effect rigis, we need a quick grounding in electrical physics. 61 00:03:05.199 --> 00:03:06.439 Right, voltage and current. 62 00:03:06.840 --> 00:03:09.879 Okay, let's unpack this. Using one of the classic analogies 63 00:03:09.879 --> 00:03:14.080 from Comer's text, we can visualize this basic circuit as. 64 00:03:14.000 --> 00:03:16.680 Plumbing right, a very helpful way to think about it. 65 00:03:16.719 --> 00:03:19.719 So, voltage is the potential energy which acts like water 66 00:03:19.759 --> 00:03:22.919 pressure in the pipes, and current is the actual flow 67 00:03:22.960 --> 00:03:24.639 of the water the electrons through. 68 00:03:24.439 --> 00:03:29.759 Those pipes exactly. And the moss fat then introduces three 69 00:03:30.120 --> 00:03:33.599 distinct terminals into that plumbing system. You have a source, 70 00:03:33.680 --> 00:03:36.319 a drain, and a gate. Okay, the sort and the 71 00:03:36.400 --> 00:03:38.719 drain act as the two ends of your main water 72 00:03:38.800 --> 00:03:41.439 pipe where the current actually wants to flow, and the 73 00:03:41.520 --> 00:03:44.039 gate is positioned between them, acting as a valve. 74 00:03:44.319 --> 00:03:46.960 Okay, but here's where my understanding gets a little fuzzy though. 75 00:03:47.639 --> 00:03:50.680 If the gate is a valve, what physically turns it? 76 00:03:50.960 --> 00:03:51.400 Ah? 77 00:03:51.599 --> 00:03:54.319 Because like with a mechanical relay, you have a physical 78 00:03:54.319 --> 00:03:57.360 electromagnet pulling a switch, and with the vacuum tube you 79 00:03:57.400 --> 00:04:00.599 have heat. But with a moss fat, how does electricity 80 00:04:00.639 --> 00:04:02.960 act as its own hand? To turn the valve off 81 00:04:03.000 --> 00:04:03.199 and on? 82 00:04:03.560 --> 00:04:06.159 It relies on an electric field, hence the name field 83 00:04:06.159 --> 00:04:10.680 effect transistor. Yeah. So when you apply a specific voltage 84 00:04:10.759 --> 00:04:14.879 to that gate terminal, it generates an electric field that 85 00:04:14.919 --> 00:04:17.959 physically alters the properties of the silicon below it. 86 00:04:18.240 --> 00:04:20.759 Wait, it physically changes the silicon. 87 00:04:20.439 --> 00:04:24.360 Well, electrically alters it. It pulls electrons into a channel 88 00:04:24.639 --> 00:04:27.839 and suddenly that lowers the electrical resistance between the source 89 00:04:27.879 --> 00:04:30.560 and the drain, so the current can now flow. 90 00:04:30.639 --> 00:04:31.000 Wow. 91 00:04:31.279 --> 00:04:33.480 And then when you drop the voltage at the gate, 92 00:04:33.639 --> 00:04:37.360 the field collapses, the resistance spikes back up, and the 93 00:04:37.399 --> 00:04:40.600 flour just starps. So it's a completely non mechanical switch 94 00:04:40.720 --> 00:04:42.720 controlled purely by potential energy. 95 00:04:42.839 --> 00:04:45.279 That is brilliant. It just eliminates the physical wear and 96 00:04:45.319 --> 00:04:51.160 tear entirely exactly. And modern chips use CMOS technology right, 97 00:04:51.199 --> 00:04:55.279 complimentary metaloxide semiconductor. My understanding is that this relies on 98 00:04:55.480 --> 00:04:59.560 pairing two different types of these transistors together to manage 99 00:04:59.600 --> 00:05:00.560 power efficiently. 100 00:05:00.800 --> 00:05:05.000 Yes, because power management is absolutely critical when you have billions. 101 00:05:04.480 --> 00:05:07.279 Of these things right, otherwise your phone would just melt literally. 102 00:05:07.360 --> 00:05:10.240 So in a CMOS setup, you pair a transistor that 103 00:05:10.279 --> 00:05:12.959 turns on when voltage is high with one that turns 104 00:05:12.959 --> 00:05:16.639 on when voltage is low. This complementary pairing guarantees that 105 00:05:16.759 --> 00:05:19.759 in any stable state, one of the transistors is. 106 00:05:19.720 --> 00:05:20.879 Always off oh ICEE. 107 00:05:20.879 --> 00:05:24.319 So it's like a seesaw exactly. And because one is 108 00:05:24.480 --> 00:05:28.079 always blocking the path to ground, the circuit draws virtually 109 00:05:28.319 --> 00:05:32.399 zero static power. It only consumes significant energy during the 110 00:05:32.439 --> 00:05:35.720 microscopic fraction of a second when it is actively switching steats. 111 00:05:36.079 --> 00:05:39.560 That is incredibly elegant. So okay, we have our highly 112 00:05:39.560 --> 00:05:43.560 efficient non mechanical switch. But a switch just lets current 113 00:05:43.600 --> 00:05:46.639 through or stops it, right, that is just routing. How 114 00:05:46.639 --> 00:05:51.000 do we cross the bridge from routing plumbing to actual logic. 115 00:05:51.120 --> 00:05:54.920 Well, we assign Boolean meaning to the physical voltage, okay. 116 00:05:54.920 --> 00:05:58.240 Explain that by convention, a lack of voltage zero volts 117 00:05:58.279 --> 00:06:01.920 physically represents a Booleon full or a binary zero. Got it, 118 00:06:02.160 --> 00:06:05.160 And a positive voltage typically something like five volts in 119 00:06:05.199 --> 00:06:08.279 older systems, or even less than a volt in modern processors, 120 00:06:08.519 --> 00:06:11.480 represents a Booleian true or a binary one. Okay. 121 00:06:11.480 --> 00:06:15.399 So by wiring these transistors together in specific physical configurations, 122 00:06:15.720 --> 00:06:19.639 we create logic gates, the fundamental building blocks, right like 123 00:06:19.839 --> 00:06:22.079 A and D or are a not. So a knot 124 00:06:22.120 --> 00:06:25.839 gate or an inverter just flips the input positive voltage 125 00:06:25.920 --> 00:06:29.800 in yield zero volts out and vice versa. And comer 126 00:06:29.839 --> 00:06:32.600 points out that a knot gate only requires two of 127 00:06:32.639 --> 00:06:34.920 those complementary transistors we just talked about. 128 00:06:35.040 --> 00:06:36.920 Yeah, it's very simple, But then you also have the 129 00:06:36.959 --> 00:06:40.360 a and D gate, requiring both inputs to be positive 130 00:06:40.399 --> 00:06:43.240 to output a positive voltage, and the O R gate, 131 00:06:43.480 --> 00:06:47.199 where either input being positive triggers a positive output. But 132 00:06:47.319 --> 00:06:50.839 what's fascinating here is a disconnect between software design and 133 00:06:50.920 --> 00:06:51.560 hardware design. 134 00:06:51.680 --> 00:06:53.600 Oh yeah, I noticed this in the text. 135 00:06:53.480 --> 00:06:57.439 Right, because software engineers think natively in d and or logic, 136 00:06:57.759 --> 00:07:01.800 but at the hardware level, engineer's strong prefer nand meaning 137 00:07:01.959 --> 00:07:03.720 not and nore gates. 138 00:07:04.079 --> 00:07:06.560 Yeah, it seemed entirely counterintuitive to me. I mean, why 139 00:07:06.560 --> 00:07:09.319 would you want to build an architecture based on negative logic? 140 00:07:09.720 --> 00:07:12.000 Just makes the boolean expressions far more difficult to read. 141 00:07:12.120 --> 00:07:14.600 It does, but the preference is strictly dictated by the 142 00:07:14.600 --> 00:07:18.639 physical reality of the transistors. Building a nandgate is physically 143 00:07:18.720 --> 00:07:20.759 simpler and faster than building an ang gate. 144 00:07:20.920 --> 00:07:21.959 Wait really faster? 145 00:07:22.040 --> 00:07:26.480 How well? A nandgate only requires four transistors, But because 146 00:07:26.480 --> 00:07:29.800 an angate naturally outputs the inverted signal based on how 147 00:07:29.839 --> 00:07:33.519 the CMOS transistors are arranged, building a true andy gate 148 00:07:33.600 --> 00:07:35.759 actually requires building a nangate first. 149 00:07:36.000 --> 00:07:36.439 Oh wow. 150 00:07:36.680 --> 00:07:38.839 Yeah, and then you have to wire an additional two 151 00:07:38.920 --> 00:07:41.720 transistor not gate to the end of it just to 152 00:07:41.759 --> 00:07:43.759 flick the signal back to positive logic. 153 00:07:43.879 --> 00:07:47.160 So it's six transistors instead of four exactly, So it 154 00:07:47.160 --> 00:07:50.360 takes more physical components, more space, and more power just 155 00:07:50.399 --> 00:07:54.560 to get the positive logic right. That physical cost directly 156 00:07:54.600 --> 00:07:56.759 shapes the logical architecture. 157 00:07:56.439 --> 00:07:58.519 That is so interesting. It actually reminds me of the 158 00:07:58.560 --> 00:08:01.800 classic seventy four hundre undred family of TTL chips, the 159 00:08:03.120 --> 00:08:06.360 Transistor Logic series. Oh classic, yeah, for anyone who has 160 00:08:06.399 --> 00:08:09.120 ever built a hobbyist circuit board, these are the little 161 00:08:09.160 --> 00:08:12.519 black rectangular plastic chips with metal legs sticking out fourteen 162 00:08:12.560 --> 00:08:14.600 pin dip or duel in line package. 163 00:08:14.720 --> 00:08:17.240 Right. The seventy four hundred chip is the quintessential example 164 00:08:17.319 --> 00:08:18.639 of early digital. 165 00:08:18.319 --> 00:08:22.120 Logic packaging because inside that single tiny plastic box you 166 00:08:22.199 --> 00:08:24.519 literally just have four independent man gates. 167 00:08:24.839 --> 00:08:27.839 You have pins for power and ground to run the chip, 168 00:08:28.160 --> 00:08:31.079 and the remaining pins are simply the physical inputs and 169 00:08:31.120 --> 00:08:35.279 outputs for those four gates. It makes the abstract concept 170 00:08:35.279 --> 00:08:37.000 of a truth table very real. 171 00:08:37.159 --> 00:08:38.240 It really does, because you. 172 00:08:38.240 --> 00:08:42.320 Can physically measure the voltage on pin three based on 173 00:08:42.480 --> 00:08:44.399 what voltage you applied to pins one. 174 00:08:44.279 --> 00:08:47.519 And two, And those truth tables are the map engineers 175 00:08:47.600 --> 00:08:50.879 used to verify that the physical layout of these transistors 176 00:08:50.919 --> 00:08:54.720 will perfectly execute a specific boolean expression like checking your 177 00:08:54.759 --> 00:08:58.720 math exactly. You map every possible combination of high and 178 00:08:58.759 --> 00:09:01.519 low voltage inputs to get guarantee the output matches your 179 00:09:01.559 --> 00:09:02.639 logical intent. 180 00:09:02.519 --> 00:09:05.919 Which we desperately need because having dates that can perform 181 00:09:05.960 --> 00:09:08.320 basic logic like if a is true and b is 182 00:09:08.360 --> 00:09:10.919 false isn't quite enough to run software. 183 00:09:11.080 --> 00:09:11.600 No, it's not. 184 00:09:11.879 --> 00:09:14.120 At some level, the computer must be able to perform 185 00:09:14.200 --> 00:09:17.000 actual arithmetic. I mean, it has to add binary numbers together. 186 00:09:17.120 --> 00:09:19.879 Right, And this moves us into combinatorial circuits, where we 187 00:09:19.919 --> 00:09:23.440 combine multiple gates to create a more complex direct output. 188 00:09:23.799 --> 00:09:27.159 So to add two single binary bits together, say a 189 00:09:27.240 --> 00:09:30.399 one in a one, which in binary results in a 190 00:09:30.519 --> 00:09:32.919 zero with a carried one, we use a circuit called 191 00:09:32.960 --> 00:09:33.559 a half adder. 192 00:09:33.679 --> 00:09:35.840 Okay, So the half adder takes two bits as input 193 00:09:36.120 --> 00:09:38.080 and needs to output a some bit and a carry 194 00:09:38.080 --> 00:09:41.000 bit correct, So it splits the input signal down two paths. 195 00:09:41.159 --> 00:09:45.000 One path goes into an XR gate an exclusive or gate. 196 00:09:45.200 --> 00:09:49.559 Right, and remember the xor only outputs true if one 197 00:09:49.600 --> 00:09:51.559 input is true, but not both. 198 00:09:51.679 --> 00:09:53.799 Okay, So one closed zero outputs a one yes, but 199 00:09:53.919 --> 00:09:55.960 one plus one outputs a zero exactly. 200 00:09:56.080 --> 00:09:59.080 That handles the sum portion, got it, But what about 201 00:09:59.120 --> 00:10:02.600 the carry well Well, simultaneously, the other path feeds those 202 00:10:02.600 --> 00:10:05.639 same two inputs into a standard A and D gate 203 00:10:05.759 --> 00:10:07.039 to compute the carry bit. 204 00:10:07.600 --> 00:10:10.200 Ah, because a binary edition only carries a one to 205 00:10:10.240 --> 00:10:13.039 the next column if both input A and input B 206 00:10:13.159 --> 00:10:15.600 are true precisely. Okay, so a half adder handles a 207 00:10:15.600 --> 00:10:18.480 single column perfectly, but any column past the first one 208 00:10:18.559 --> 00:10:20.519 might have to deal with a carry bit coming over 209 00:10:20.519 --> 00:10:21.120 from the right. 210 00:10:21.120 --> 00:10:23.240 Right, So it needs to add three inputs bit A, 211 00:10:23.519 --> 00:10:25.200 bit B and the carry. 212 00:10:24.879 --> 00:10:26.960 In bit, which means we need something more complex. 213 00:10:27.240 --> 00:10:30.039 Yes, that requires a full adder. Oh and it is 214 00:10:30.120 --> 00:10:34.240 constructed by physically wiring two half adders together along with 215 00:10:34.320 --> 00:10:37.519 an O R gate to resolve the final carryout signal. 216 00:10:37.840 --> 00:10:38.480 That makes sense. 217 00:10:38.600 --> 00:10:41.039 And if we connect this to the bigger picture, this 218 00:10:41.159 --> 00:10:45.480 specific arrangement of logic gates represents a profound conceptual threshold. 219 00:10:45.679 --> 00:10:48.559 How so we are no longer just manipulating water pressure 220 00:10:48.559 --> 00:10:51.440 in a pipe. By layering truth tables and combining gates, 221 00:10:51.480 --> 00:10:53.519 we have actually engineered a machine. 222 00:10:53.120 --> 00:10:56.799 That computes Wow. Yeah, the modularity of it is what 223 00:10:56.879 --> 00:10:59.639 strikes me, because if you are designing a thirty two 224 00:10:59.720 --> 00:11:04.840 bit processor. You don't have to invent a monolithic, wildly 225 00:11:04.919 --> 00:11:07.600 complex circuit to add thirty two bit numbers. Oh not 226 00:11:07.600 --> 00:11:10.600 at all. You just take that single full add or blueprint, 227 00:11:10.840 --> 00:11:14.360 physically replicate it thirty two times on the silicon, and 228 00:11:14.480 --> 00:11:16.960 chain them side by side. The carry out wire of 229 00:11:17.000 --> 00:11:20.039 column one connects directly to the carrying wire of column. 230 00:11:19.759 --> 00:11:22.320 Two, exactly. It is endlessly scalable. 231 00:11:22.440 --> 00:11:23.200 That's incredible. 232 00:11:23.240 --> 00:11:26.919 The architecture scales beautifully, and the sum cascades down the 233 00:11:27.000 --> 00:11:29.159 chain of adders almost instantaneously. 234 00:11:29.519 --> 00:11:32.600 But wait here is a critical flaw. We have a 235 00:11:32.639 --> 00:11:35.720 circuit that can add two thirty two bit numbers. The 236 00:11:35.720 --> 00:11:39.600 inputs are active, the voltage campcades through, and the sum 237 00:11:39.600 --> 00:11:42.159 appears on the output wires right. But the second you 238 00:11:42.240 --> 00:11:46.240 drop the voltage on those input pins, the sum vanishes. 239 00:11:46.720 --> 00:11:51.440 It does the circuit has total amnesia because combinatorial circuits 240 00:11:51.440 --> 00:11:54.679 only reflect their current inputs. So how can a computer 241 00:11:54.799 --> 00:11:57.840 possibly function if it can't remember the result of its 242 00:11:57.840 --> 00:11:58.399 own math? 243 00:11:58.600 --> 00:12:01.039 Ah? Well, memory requires there's a different kind of circuit 244 00:12:01.200 --> 00:12:04.759 entirely called a sequential circuit. Okay, and creating memory out 245 00:12:04.799 --> 00:12:08.440 of logic gates relies on a really fascinating physical quirk 246 00:12:08.519 --> 00:12:10.639 of the hardware called propagation delay. 247 00:12:10.759 --> 00:12:13.039 Wait, let me sell you there, Because if you wire 248 00:12:13.080 --> 00:12:15.799 and not gates output directly back into its own input, 249 00:12:16.000 --> 00:12:19.080 shouldn't that create a logical paradox that just fries the circuit? 250 00:12:19.159 --> 00:12:21.559 It seems like it would, right, yeah, Because. 251 00:12:21.279 --> 00:12:24.000 If the input is one, the output becomes zero, which 252 00:12:24.000 --> 00:12:26.159 feeds back and makes the input zero, which makes the 253 00:12:26.159 --> 00:12:28.919 output one. It should instantly short itself. 254 00:12:28.559 --> 00:12:31.600 Out right in a world of perfect instantaneous logic, it 255 00:12:31.600 --> 00:12:35.080 would absolutely be a paradox. But physical hardware is bound 256 00:12:35.080 --> 00:12:38.440 by the speed of electrons. When the input voltage changes 257 00:12:38.480 --> 00:12:41.639 on a gate, it takes a tiny fraction of the second, 258 00:12:41.759 --> 00:12:44.879 perhaps just a few peico seconds in modern chips, for 259 00:12:44.960 --> 00:12:48.200 the transistors to actually change state and the output voltage 260 00:12:48.240 --> 00:12:48.720 to settle. 261 00:12:48.919 --> 00:12:51.039 And that is propagation delay exactly. 262 00:12:51.080 --> 00:12:52.519 That is propagation delay. 263 00:12:52.639 --> 00:12:55.480 So, because it takes a microscopic moment for the water 264 00:12:55.600 --> 00:12:58.879 to travel through the newly open valve, the paradox doesn't 265 00:12:58.879 --> 00:13:01.960 destroy the circuit, yep, it causes it to oscillate. It 266 00:13:02.000 --> 00:13:06.159 physically flips back and forth between zero and one, generating a. 267 00:13:06.159 --> 00:13:09.879 Square wave yes, and we harness that physical delay to 268 00:13:09.919 --> 00:13:13.279 create a stable memory circuit called a latch. Okay, the 269 00:13:13.279 --> 00:13:16.320 most basic latch uses four nand gates arranged with a 270 00:13:16.320 --> 00:13:19.480 feedback loop. Two of the gates have their outputs wired 271 00:13:19.480 --> 00:13:22.799 directly back into each other's inputs, and it also features 272 00:13:22.840 --> 00:13:24.759 a data line and an enable line. 273 00:13:24.799 --> 00:13:27.879 Here's where it gets really interesting, because I find it 274 00:13:27.960 --> 00:13:31.720 helpful to visualize the latch as a VIP room at 275 00:13:31.759 --> 00:13:32.759 an exclusive club. 276 00:13:32.879 --> 00:13:33.600 Oh I like this. 277 00:13:34.080 --> 00:13:36.559 So the enable line acts as the bouncer at the door, 278 00:13:37.039 --> 00:13:39.720 and the data line is the VIP trying to get inside. 279 00:13:39.960 --> 00:13:42.960 When the bouncer opens the door, meaning when the enable 280 00:13:43.039 --> 00:13:46.639 line receives a high voltage, the data flows right through 281 00:13:47.279 --> 00:13:50.480 the output of the room perfectly matches whatever VIP is 282 00:13:50.519 --> 00:13:51.759 standing at the door exactly. 283 00:13:51.840 --> 00:13:54.840 It acts completely transparently as long as the enable line 284 00:13:54.879 --> 00:13:55.360 is held. 285 00:13:55.240 --> 00:13:58.559 High, right. But when the bouncer closes the door, when 286 00:13:58.559 --> 00:14:02.000 the enabled voltage drops back to zero, the data is 287 00:14:02.039 --> 00:14:03.960 trapped inside the VIP room. 288 00:14:04.120 --> 00:14:04.840 It's locked in. 289 00:14:05.039 --> 00:14:07.879 Yeah. Even if a totally different signal shows up on 290 00:14:07.919 --> 00:14:11.240 the data line outside, the output of the VIP room 291 00:14:11.440 --> 00:14:14.279 refuses to change. It is officially saved. The state. 292 00:14:14.720 --> 00:14:17.879 That's a great analogy because the feedback loop between those 293 00:14:17.960 --> 00:14:20.559 nangates locks them into a stable configuration. 294 00:14:20.840 --> 00:14:21.200 Wow. 295 00:14:21.279 --> 00:14:23.879 Once the enable line drops, they essentially hold each other 296 00:14:23.879 --> 00:14:27.279 in place infinitely, remembering that final voltage state until the 297 00:14:27.360 --> 00:14:28.519 enable line is opened again. 298 00:14:28.639 --> 00:14:29.720 That's just so clever. 299 00:14:29.840 --> 00:14:31.879 And if you wire sixty four of these one bit 300 00:14:31.960 --> 00:14:35.120 latches together in parallel, sharing a single enable line, you 301 00:14:35.159 --> 00:14:38.080 have just built a sixty four bit register, which is. 302 00:14:38.039 --> 00:14:39.799 The fast short term memory of a CPU. 303 00:14:39.960 --> 00:14:41.480 Exactly, You now have memory. 304 00:14:41.720 --> 00:14:46.120 Okay, So we have logic to process the data, adders 305 00:14:46.159 --> 00:14:48.360 to do the math, and registers to store the result. 306 00:14:48.559 --> 00:14:51.279 We basically have all the pieces for a computer. We do, 307 00:14:51.879 --> 00:14:55.039 But there's a glaring automation problem here. Oh yes, when 308 00:14:55.080 --> 00:14:57.759 you compile and run a program, a human being isn't 309 00:14:57.799 --> 00:15:01.639 sitting on the motherboard manually the enable line on these 310 00:15:01.679 --> 00:15:05.519 registers billions of times a second to move data from 311 00:15:05.559 --> 00:15:06.960 the adder into memory. 312 00:15:07.080 --> 00:15:09.360 No, they certainly aren't. And that's because a standard latch 313 00:15:09.480 --> 00:15:12.480 is level sensitive, meaning it stays open as long as 314 00:15:12.480 --> 00:15:15.960 the enable line is high. Okay. To automate the flow 315 00:15:15.960 --> 00:15:18.960 of data without human intervention, you need a circuit that 316 00:15:19.039 --> 00:15:22.159 reacts to a transition rather than a steady state. Got it, 317 00:15:22.600 --> 00:15:25.320 So we construct a more complex component called a flip flop. 318 00:15:25.679 --> 00:15:28.240 So how does a flip flop differ from a standard 319 00:15:28.279 --> 00:15:29.440 latch in practice? 320 00:15:29.480 --> 00:15:31.639 Well, a flip flop is edge triggered edge triggered. 321 00:15:31.679 --> 00:15:31.840 Right. 322 00:15:31.879 --> 00:15:34.759 It only captures the data at the exact microscopic moment 323 00:15:34.879 --> 00:15:37.399 the enable signal transitions from low to high. 324 00:15:37.480 --> 00:15:38.039 Oh I see. 325 00:15:38.120 --> 00:15:41.240 It ignores the data line completely when the enabled signal 326 00:15:41.279 --> 00:15:44.000 is resting at zero, and it ignores it when it 327 00:15:44.080 --> 00:15:46.879 is resting at one. It only opens and shuts its 328 00:15:46.960 --> 00:15:49.639 door on the upward strike of the voltage spike. 329 00:15:49.480 --> 00:15:53.039 Like a push button toggle rather than a sustained lever. Precisely. Okay, 330 00:15:53.039 --> 00:15:55.600 So by striking a series of flip flops together so 331 00:15:55.679 --> 00:15:58.039 the output of one feeds the input of the next, 332 00:15:58.679 --> 00:16:01.960 you create a binary count. Yes, every time a voltage 333 00:16:01.960 --> 00:16:05.720 pulse hits the first flip flop, the counter increments its 334 00:16:05.720 --> 00:16:09.320 binary value, so it can automatically step through a sequence 335 00:16:09.320 --> 00:16:10.039 of instructions. 336 00:16:10.240 --> 00:16:13.480 But this raises an important question regarding synchronization. 337 00:16:13.720 --> 00:16:14.600 Okay, that's that. 338 00:16:14.879 --> 00:16:18.960 Well, you have millions of logic gates, thousands of adders, 339 00:16:18.960 --> 00:16:22.600 and hundreds of registers and they are all physically scattered 340 00:16:22.600 --> 00:16:25.399 across a silicon die, so they all have slightly different 341 00:16:25.440 --> 00:16:28.600 propagation delays depending on how far the electrons literally have 342 00:16:28.679 --> 00:16:31.360 to travel. Oh man, yeah, So how do you guarantee 343 00:16:31.360 --> 00:16:34.600 the data has fully cascaded through the adder and settled 344 00:16:34.600 --> 00:16:37.279 on the correct sum before the register's flip flop is 345 00:16:37.279 --> 00:16:38.240 triggered to save it? 346 00:16:38.559 --> 00:16:41.559 Because if the flip flop fires too early, it saves 347 00:16:41.559 --> 00:16:44.120 the garbage data that is still mid calculation exactly. 348 00:16:44.159 --> 00:16:46.519 The entire system would just descend into chaos. 349 00:16:46.679 --> 00:16:47.480 So what's the solution. 350 00:16:47.639 --> 00:16:50.360 The solution is the ultimate coordinator, the clock. 351 00:16:50.559 --> 00:16:54.559 The clock. We hear about clock speed constantly when buying 352 00:16:54.559 --> 00:16:57.840 a computer, right, like three gigaherds, four gigarherds. Right, But 353 00:16:58.039 --> 00:16:59.799 it isn't keeping time of day. 354 00:17:00.200 --> 00:17:03.480 No, not at all. A computer's clock is an oscillating 355 00:17:03.519 --> 00:17:05.359 circuit acting as a digital heartbeat. 356 00:17:05.640 --> 00:17:06.079 Heartbeat. 357 00:17:06.279 --> 00:17:10.240 Yes, it sends out a continuous, perfectly regular pulse of 358 00:17:10.359 --> 00:17:13.960 alternating high and low voltage across the entire chip. Okay, 359 00:17:14.279 --> 00:17:17.960 every flipplop, every sequence in the processor is wired to 360 00:17:18.039 --> 00:17:21.440 listen to that single clock signal. They are strictly designed 361 00:17:21.480 --> 00:17:24.359 to only change state or latch data on the rising 362 00:17:24.440 --> 00:17:26.359 edge of that specific clock pulse. 363 00:17:26.440 --> 00:17:28.920 Wow. So it forces order onto the physical chaos of 364 00:17:28.920 --> 00:17:31.599 the electrons exactly. So, if a processor has a clock 365 00:17:31.640 --> 00:17:35.480 speat of four gigahertz, that heartbeat is pulsing four billion 366 00:17:35.519 --> 00:17:38.480 times a second, which means the physical electricity must flow 367 00:17:38.519 --> 00:17:42.400 through all the logic gates, compute the math, travel down 368 00:17:42.400 --> 00:17:45.039 the wire, and arrive at the memory register in less 369 00:17:45.079 --> 00:17:48.319 than zero point twenty five nanoseconds before the next clock 370 00:17:48.400 --> 00:17:49.000 pulse hits. 371 00:17:49.200 --> 00:17:52.480 It guarantees that all the combinatorial circuits have had enough 372 00:17:52.519 --> 00:17:55.880 time to finish their physical work before the sequential circuits 373 00:17:55.920 --> 00:17:58.480 lock in the results and the processor moves to the 374 00:17:58.519 --> 00:17:59.160 next instruction. 375 00:17:59.319 --> 00:18:00.880 That is stagger it is. 376 00:18:01.039 --> 00:18:03.880 It allows the machine to run totally on autopilot. 377 00:18:04.160 --> 00:18:06.400 So what does this all mean for you listening to 378 00:18:06.440 --> 00:18:09.640 this deep dive? We started by talking about water pressure 379 00:18:09.640 --> 00:18:12.519 and pipes, and we ended up with a four gigahertz 380 00:18:12.720 --> 00:18:17.240 digital heartbeat synchronizing millions of sequential operations. It's quite a journey, 381 00:18:17.319 --> 00:18:21.480 it is. But understanding this physical hardware reality makes you 382 00:18:21.519 --> 00:18:22.920 a tangibly better programmer. 383 00:18:22.960 --> 00:18:23.720 Oh absolutely. 384 00:18:23.799 --> 00:18:27.440 It ceases to be abstract magic when you realize every 385 00:18:27.440 --> 00:18:31.079 line of code you write must eventually route physical electricity 386 00:18:31.119 --> 00:18:34.920 through logic gates and wait for propagation delays. It changes 387 00:18:34.920 --> 00:18:36.319 how you architect systems. 388 00:18:36.440 --> 00:18:39.759 It definitely encourages tighter, more efficient code, right. 389 00:18:39.920 --> 00:18:43.440 And it provides vital insight when you are debugging complex 390 00:18:43.480 --> 00:18:44.720 performance issues. 391 00:18:44.519 --> 00:18:47.119 Because the efficiency of your code directly translates to the 392 00:18:47.119 --> 00:18:50.680 physical workload of the machine exactly. But you know it 393 00:18:50.720 --> 00:18:52.680 also leads us right back to the physical limits we 394 00:18:52.720 --> 00:18:53.640 discussed at the start of. 395 00:18:53.640 --> 00:18:55.920 The show, the quantum tunneling right. 396 00:18:56.119 --> 00:18:59.559 Because the text touches on Moore's law and heat dissipation. 397 00:19:00.440 --> 00:19:04.000 The entire strategy for making a computer compute faster is 398 00:19:04.039 --> 00:19:05.519 to increase the clock speed. 399 00:19:05.920 --> 00:19:08.400 You want the heartbeat to pulse faster, yes. 400 00:19:08.599 --> 00:19:11.960 But to achieve that without the system failing, you must 401 00:19:12.039 --> 00:19:15.400