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<v Speaker 1>Welcome to this deep dive. Today. We're digging into analog

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<v Speaker 1>circuit design, specifically around the year twenty ten.

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<v Speaker 2>Yeah, we've got this great collection of discussions from the

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<v Speaker 2>ACD workshop back.

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<v Speaker 1>Then, and our mission really is to pull out the

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<v Speaker 1>key developments the future ideas across well three main areas.

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<v Speaker 2>That's robust design, Sigma delta converters, and RFID exactly.

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<v Speaker 1>Think of this as like your shortcut to understanding some

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<v Speaker 1>pretty complex stuff without getting totally bogged down. You might

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<v Speaker 1>find some surprising things here.

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<v Speaker 2>It's a fascinating snapshot. Really, twenty ten was a pivotal moment.

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<v Speaker 2>Nanoscale CMOS was becoming real.

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<v Speaker 1>Which open doors but also threw up new roadblocks totally.

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<v Speaker 2>So we'll look at how engineers were tackling robustness in

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<v Speaker 2>that new world, the cool stuff happening in data conversion

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<v Speaker 2>with signa deltas, and you know, the whole RFID universe

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<v Speaker 2>started to expand.

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<v Speaker 1>Perfect. Okay, let's start with robust design. That was clearly

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<v Speaker 1>a huge theme. Everyone was pushing for smaller features, you know,

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<v Speaker 1>ninety nimeters even smaller, and.

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<v Speaker 2>That unlocked amazing things. But yeah, the obstacles were real.

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<v Speaker 2>It's where the physics, the tiny atomic level stuff really

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<v Speaker 2>started hitting circuit design hard.

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<v Speaker 1>So engineers couldn't just use the old bulk models anymore.

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<v Speaker 2>Pretty much, the designs got way more complex, which stretched

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<v Speaker 2>out time to market. And then there's the variability. The

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<v Speaker 2>transitionors themselves just weren't perfectly identical.

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<v Speaker 1>Anymore, leading to mismatch, lower yields.

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<v Speaker 2>Exactly, and reliability over time became a bigger worry too,

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<v Speaker 2>things like hot carriers NbTi. Basically the circuits degrading.

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<v Speaker 1>Negative bias, temperature instability. That one sounds like a nightmare

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<v Speaker 1>for designers. And you mentioned even the physical layout got trick.

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<v Speaker 2>Here, Oh yeah, more rules, tighter constraints, and these optical

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<v Speaker 2>proximity effects started messing with the shapes they were trying

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<v Speaker 2>to print on the silicon.

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<v Speaker 1>So the manufacturing process itself added challenges. But robustness wasn't

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<v Speaker 1>just about nanoscale, was it. There was this push for

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<v Speaker 1>circuits and really tough environments too.

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<v Speaker 2>Absolutely a big one was high temp, high voltage electronics,

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<v Speaker 2>I think electric and hybrid vehicles which were just starting

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<v Speaker 2>to take off. Their challenge there was making sure everything

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<v Speaker 2>worked together reliably. The silicon, the packaging the materials. It

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<v Speaker 2>needed complex simulations, thermal electric stuff, reliability calculations, especially for

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<v Speaker 2>the smart power modules.

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<v Speaker 1>And they were making real progress. I saw mentions of

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<v Speaker 1>igbt's handling pretty extreme temperatures.

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<v Speaker 2>Yeah, junction temps up to one hundred and seventy five

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<v Speaker 2>degree C, sometimes even near two hundred C in short

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<v Speaker 2>circuit tests.

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<v Speaker 1>Wow, that's incredibly hot. Must have involved some serious trade

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<v Speaker 1>offs between cooling and performance for sure.

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<v Speaker 2>And this need for high temp electronics wasn't just in

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<v Speaker 2>the main powertrain. It was sensors, motors all over the.

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<v Speaker 1>Vehicle, different power levels, different integration approaches.

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<v Speaker 2>Right, monolithic versus multi chip modules. Yeah, that was a

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<v Speaker 2>big decision point for reliability too. The whole thing was

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<v Speaker 2>guided by tough auto industry standards like AECQ one oh one.

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<v Speaker 1>It makes sense make sure your car works reliably hot

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<v Speaker 1>or cold, Okay. Another hostile environment mentioned was radiation space

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<v Speaker 1>for example. That sounds totally different it is.

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<v Speaker 2>You've got cumulative damage over time and also these single

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<v Speaker 2>hits from hy energy particles.

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<v Speaker 1>Nasty stuff.

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<v Speaker 2>But what's interesting is that researchers were finding ways to

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<v Speaker 2>use standard commercial CMOS. Turns out with the gate oxides

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<v Speaker 2>getting thinner, like around five nanometers. Yeah, the threshold voltage

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<v Speaker 2>shift from radiation became almost negligible for a lot of uses.

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<v Speaker 1>Really, so you didn't always need special expensive rad hard processes.

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<v Speaker 2>Not always. It wasn't perfect, mind you. There were still

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<v Speaker 2>issues like with the STI oxide leakage varying a lot.

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<v Speaker 1>Okay, so still burdles.

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<v Speaker 2>But they developed clever layout tricks, things like ring sources

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<v Speaker 2>guard rings basically protective structures around their transistors.

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<v Speaker 1>To shield them a bit sort of.

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<v Speaker 2>Yeah, improve the tolerance to the total radiation dose. And

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<v Speaker 2>then for those single particle hits, especially in memory.

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<v Speaker 1>Like bitflips and surround exactly.

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<v Speaker 2>They use techniques like redundancy special cell designs like the

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<v Speaker 2>Whittaker cell DICE architectures, although DICE E was showing limits

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<v Speaker 2>in newer technologies.

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<v Speaker 1>And things like triple modular redundancy error correction codes.

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<v Speaker 2>Yeah, TMR and EEDAC were key strategies too, especially for

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<v Speaker 2>protecting against those single event upsets.

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<v Speaker 1>Okay, some smart design to fight back against cosmic rays fascinating.

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<v Speaker 1>And the third tough environment electromagnetic compatibility EMC.

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<v Speaker 2>Especially for power switches.

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<v Speaker 1>Absolutely critical. You pack more and more electronics into a car.

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<v Speaker 1>They can't interfere with each other. That's a safety thing, right.

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<v Speaker 1>So the trend was towards simulating this stuff earlier, using

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<v Speaker 1>techniques like direct power injection testing, but doing it in

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<v Speaker 1>the simulation world to.

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<v Speaker 2>Predict problems before building.

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<v Speaker 1>The chip exactly. And a key technique was optimizing the

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<v Speaker 1>impedance of the pins on those smart power switches to

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<v Speaker 1>make them less susceptible. So designing the chip to be

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<v Speaker 1>a good neighbor in that noisy electrical environment makes sense. Okay,

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<v Speaker 1>shifting focus a bit, let's talk reliability more broadly in

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<v Speaker 1>nanoscale cmos, not just extreme conditions but everyday stress.

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<v Speaker 2>Right, So a big part was modeling that long term

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<v Speaker 2>degradation hot carriers and BTI.

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<v Speaker 1>Again, how do they model it.

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<v Speaker 2>They'd simulate how transistors behaved under typical signal stress and

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<v Speaker 2>then use models to kind of extrapolate how much they'd

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<v Speaker 2>degrade over the chip's.

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<v Speaker 1>Lifetime, like accelerated aging, but in simulation pretty much.

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<v Speaker 2>Yeah, helps find the weak spots early.

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<v Speaker 1>Smart And what about dealing with manufacturing variations, because no

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<v Speaker 1>two chips are ever exactly the same?

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<v Speaker 2>True? That process variability was a big headache. One approach

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<v Speaker 2>was post fabrication.

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<v Speaker 1>Calibration, tuning the chip after it's made.

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<v Speaker 2>Yeah, Like the example was using switching sequence post adjustment

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<v Speaker 2>on a DC. Yeah, they could tune it up and

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<v Speaker 2>actually use less chip area to get the same accuracy.

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<v Speaker 1>Clever, And then there were techniques for adapting while the circuit.

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<v Speaker 2>Is running right runtime self adaptation. The example was a

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<v Speaker 2>lot N driver with extra backup transistors like spares kind of.

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<v Speaker 2>It had a monitor circuit that could switch in replacements

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<v Speaker 2>if others started to degrade, keeps performance.

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<v Speaker 1>Stable, but that takes up more space.

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<v Speaker 2>I guess, yeah, there's always a trade off area versus resilience.

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<v Speaker 1>Okay, Now this was also when hike metal gate technology

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<v Speaker 1>was coming in. How did that change the variability picture?

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<v Speaker 2>It was a mixed bag. It helps with some variability

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<v Speaker 2>sources like random dope fluctuations, but it introduced new ones

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<v Speaker 2>like the high material wasn't perfectly uniform, granularity issues and

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<v Speaker 2>variations in the metal gates work function.

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<v Speaker 1>So solved one problem created another.

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<v Speaker 2>A bit yeah, and things like random dope ins line

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<v Speaker 2>is roughness, polygrain boundaries. They still caused threshold voltage variations,

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<v Speaker 2>especially for the really short channel transistors.

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<v Speaker 1>The smallest ones were most sensitive.

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<v Speaker 2>They really were needed very careful design, and all this

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<v Speaker 2>complexity really flowed down into the physical design, the actual layout.

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<v Speaker 1>I bet more rules, tighter tolerances must have been tough.

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<v Speaker 2>It was. Designers maybe had less direct control over layout,

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<v Speaker 2>and those optical proximity effects corner rounding slight misalignments, they

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<v Speaker 2>caused matching errors.

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<v Speaker 1>So tiny manufacturing imperfections mattered more.

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<v Speaker 2>A lot. More strategies involve things like using only certain

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<v Speaker 2>device widths for regularity. Considering stress from metal wires.

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<v Speaker 1>Above, it sounds like circuit design and physical layout had

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<v Speaker 1>to become much more tightly integrated.

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<v Speaker 2>Absolutely planning the physical aspects early was key to avoiding

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<v Speaker 2>problems later.

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<v Speaker 1>Okay, last point on robust design, packaging and interconnects, especially

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<v Speaker 1>for those high power automotive modules where silicon meets the

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<v Speaker 1>real world exactly.

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<v Speaker 2>Multi chip modules were common in EVSAGVS, and a huge

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<v Speaker 2>issue was mechanical stress. Stress from what different materials expanding

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<v Speaker 2>and contracting at different rates when the temperature changes, you

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<v Speaker 2>know a CTE mismatch. Silicon expands differently than the ceramic

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<v Speaker 2>substrate or the base plate.

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<v Speaker 1>Ah sot up and cooling down put strain on everything.

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<v Speaker 2>Big time, especially over the wide temperature range. Cars operate

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<v Speaker 2>in like netteck of forty c up to really high temps.

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<v Speaker 1>And that affects the connections soldering wire bonds.

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<v Speaker 2>Definitely higher temps were tough on wire bonds they could

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<v Speaker 2>lift off. They did lots of power cycling tests to

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<v Speaker 2>check durability. Even the direct bond copper structures felt the

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<v Speaker 2>strain from thermal cycles.

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<v Speaker 1>Sounds like material science was just as crucial as the

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<v Speaker 1>chip design.

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<v Speaker 2>Here. It really was, and they were already looking ahead

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<v Speaker 2>exploring things like metal carbon nanotube composites from what better

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<v Speaker 2>thermal interface materials maybe even metallization. C and ts have

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<v Speaker 2>amazing thermal and electrical conductivity way better than copper. Could

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<v Speaker 2>lead to even more robust, high temp power electronics down

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<v Speaker 2>the road.

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<v Speaker 1>Interesting glimpse into the future there. Okay, that wraps up

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<v Speaker 1>robust design. Let's switch gears to our second topic. Sigma

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<v Speaker 1>delta converters essential for higher precision analog to digital conversion.

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<v Speaker 2>Yeah, and the focus here was oft and on getting

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<v Speaker 2>higher resolution your bandwidth but using less power. Constant innovation.

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<v Speaker 1>One area you highlighted was noise coupled delta sigma ADCs

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<v Speaker 1>using noise to help.

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<v Speaker 2>That sounds backward, it does, right, but the idea is

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<v Speaker 2>really clever. You take the quantization noise generated in one

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<v Speaker 2>part of the modulator.

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<v Speaker 1>The unwanded stuff.

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<v Speaker 2>Right, and you strategically inject it somewhere else in loop.

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<v Speaker 2>In certain architectures like feed forward ones, this could actually

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<v Speaker 2>boost performance without needing extra op amps.

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<v Speaker 1>Huh, what's the catch?

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<v Speaker 2>Well, you usually sacrifice a bit of the maximum input

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<v Speaker 2>signal range you can handle without distortion, so choosing the

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<v Speaker 2>quantizer resolution carefully is key. Usually need like one extra

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<v Speaker 2>bit than the modulator.

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<v Speaker 1>Order, so you're kind of using the noise against itself,

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<v Speaker 1>but you can't push it too hard. Were there different

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<v Speaker 1>ways to do this noise coupling.

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<v Speaker 2>Oh yeah, split modulators, noise canceling structures, noise coupled, time interleaved.

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<v Speaker 2>That last one. NCTI looked pretty promising. Why is that

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<v Speaker 2>it had this enhancement factor that improve things, and time

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<v Speaker 2>interleaving made it simpler to implement. Plus it was less

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<v Speaker 2>sensitive to mismatch errors between channels because it's suppressed noise

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<v Speaker 2>around the niquist frequency.

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<v Speaker 1>But there was still a trade off sq and R

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<v Speaker 1>versus robustness.

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<v Speaker 2>Always trade offs and analog design. But yeah, different ways

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<v Speaker 2>to leverage the concept.

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<v Speaker 1>Okay. Another interesting idea, very low over sampling ratio sigma

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<v Speaker 1>deltas isn't oversampling like the whole point of sigma delta.

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<v Speaker 2>It usually is, but at very low osrs they start

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<v Speaker 2>competing head to head with niquist ADCs like pipeline ADCs.

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<v Speaker 2>Really yeah, the sources suggest there's a crossover point where

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<v Speaker 2>higher order sigma deltas can actually be lower order ones.

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<v Speaker 2>Even with low osrs. You still get noise reduction even

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<v Speaker 2>with an OSR of to say.

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<v Speaker 1>Three, surprising, so you're relying more on the heavy duty

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<v Speaker 1>noise shaping even with fewer samples. How did they stack

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<v Speaker 1>up against pipelines on power? That's often critical?

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<v Speaker 2>Good question. Pipelines sometimes use these half delaying stages, which

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<v Speaker 2>could be less power efficient than masah shigma delta using

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<v Speaker 2>full period integrators. Okay, but people were working on making

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<v Speaker 2>pipelines more efficient too, swushowpams, sharing amplifiers, things like that,

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<v Speaker 2>and incremental ADCs also perform will low osrs getting good

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<v Speaker 2>resolution because they can handle bigger signals.

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<v Speaker 1>It feels like the lines between architectures were blurring a

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<v Speaker 1>bit at these low osrs. Everyone borrowing ideas.

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<v Speaker 2>Kind of yeah, optimizing for performance and power.

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<v Speaker 1>Now what about compartor based switched capacitor sigma deltas using

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<v Speaker 1>comparitors instead of op ams? Why do that.

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<v Speaker 2>Big advantage in nanoscale cmos Designing good op amps with

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<v Speaker 2>low supply voltage just gets really hard. Comparators can be simpler, faster,

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<v Speaker 2>potentially lower power.

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<v Speaker 1>Makes sense.

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<v Speaker 2>They explore different ways to build integrators with comparators. Pseudo

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<v Speaker 2>differential looked good for high speed. It cleverly turns comparator

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<v Speaker 2>delay into a common mode error, which is easier to

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<v Speaker 2>deal with later.

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<v Speaker 1>So you trade the op AMS precision for the comparator

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<v Speaker 1>speed and power benefits, then clean up them us elsewhere.

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<v Speaker 1>What about that comparator delay? Did it cause problems?

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<v Speaker 2>It could cause some output voltage overshoot, maybe a DC offset,

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<v Speaker 2>But since comparators are open loop you don't have the

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<v Speaker 2>same stability worries as with opams and feedback. The key

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<v Speaker 2>thing is just the delay time itself, which interestingly didn't

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<v Speaker 2>depend much on the filter capacitor sizes.

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<v Speaker 1>Okay, and noise was still a factor obviously.

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<v Speaker 2>Oh yeah, thermal noise from switches, reference voltages. You still

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<v Speaker 2>had to analyze all that to figure out the SNR,

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<v Speaker 2>but it was definitely a viable path, especially for low power.

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<v Speaker 1>Then there was the really different idea VCO based ADCs

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<v Speaker 1>voltage controlled oscillators.

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<v Speaker 2>Yeah, pretty novel. The VCO acts like a voltage to

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<v Speaker 2>time converter. Combine that with the time to digital converter

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<v Speaker 2>and you get noise shaping, even mismatch shaping.

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<v Speaker 1>But VCOs aren't perfectly linear, are they.

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<v Speaker 2>That's the main challenge. The relationship between input voltage and

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<v Speaker 2>output frequency isn't straight. The trick was to use the

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<v Speaker 2>phase of the VCO output as the key variable.

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<v Speaker 1>Phase.

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<v Speaker 2>Okay, theoretically that could get you really high SNDR over

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<v Speaker 2>wide bandwidths, and the prototypes mentioned showed promising results backing

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<v Speaker 2>up the theory.

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<v Speaker 1>So encoding voltage into frequency or phase a totally different

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<v Speaker 1>way to digitize cool. Lastly, wide band continuous time multi

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<v Speaker 1>bit delta sigmas using more than one bit in the quantizer.

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<v Speaker 2>That has advantages, big advantages. Multibit contizers ease the requirements

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<v Speaker 2>on the op amps, especially their SLEW rate and they

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<v Speaker 2>reduce the out of band quantization.

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<v Speaker 1>Noise leading to lower power.

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<v Speaker 2>Often yes, but the trade off is the DK in

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<v Speaker 2>the feedback loop becomes more complex. You need dynamic element

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<v Speaker 2>matching DEM to keep it.

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<v Speaker 1>Linear, right, got to make sure that this is accurate.

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<v Speaker 2>But despite that complexity, low OSR combined with multibit quantizers

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<v Speaker 2>and DEM algorithms like DWA was becoming really popular for

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<v Speaker 2>wideband stuff.

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<v Speaker 1>So trading some over sampling for multibit benefits and using

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<v Speaker 1>DEM to fix the DT sounds like a smart compromise exactly.

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<v Speaker 2>And the performance figures reported were impressive high dynamic range

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<v Speaker 2>high SNDR. They were using cascaded architectures, high speed decks,

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<v Speaker 2>really pushing the envelope.

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<v Speaker 1>Clearly, Sigma delta was a hot area for innovation back then.

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<v Speaker 2>Absolutely just relentless efforts to get better performance, less power,

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<v Speaker 2>more bandwidth, lots of creativity.

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<v Speaker 1>Okay, final topic, r FID radio frequency identification. Around twenty ten,

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<v Speaker 1>this was really starting to break out of niche uses,

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<v Speaker 1>wasn't it.

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<v Speaker 2>It really was. You know, it started way back tracking

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<v Speaker 2>nuclear stuff than cows, but by twenty ten people were

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<v Speaker 2>seriously looking at it for much broader things like what

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<v Speaker 2>tagging High value items was a big one mentioned, fashion,

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<v Speaker 2>fancy goods, electronics, huge potential for better inventory management. The

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<v Speaker 2>key was the move towards open standards that was crucial for.

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<v Speaker 1>Getting scale from cows to couture. Sounds like the market

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<v Speaker 1>was poised for growth, but maybe some hurdles remained.

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<v Speaker 2>For sure, technical issues like getting reliable reads in different environments,

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<v Speaker 2>the cost both tags and readers, and figuring out who

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<v Speaker 2>pays and who benefits the supply chain.

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<v Speaker 1>Yeah, the business side, but the.

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<v Speaker 2>Long term vision was much lower costs readers maybe two hundred,

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<v Speaker 2>passive tags just a few cents. They even talk about

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<v Speaker 2>chipless tags under a cent that was further out but revolutionary.

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<v Speaker 1>If it happened, Wow, that would make it truly everywhere.

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<v Speaker 1>Retail and consumer goods were the big targets.

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<v Speaker 2>Expected to be the largest market. Yeah. UHF was seen

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<v Speaker 2>as the main frequency for tracking objects, though HF had

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<v Speaker 2>its niches like libraries.

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<v Speaker 1>And the trend was better performance, lower cost, making it

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<v Speaker 1>essential for business.

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<v Speaker 2>That was the expectation, especially in Europe. But for that

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<v Speaker 2>kind of widespread use, standards are absolutely vital.

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<v Speaker 1>Right, and the standardization effort had started way back isoie.

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<v Speaker 2>Yeah, JTC one, SC thirty one, double G four formed

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<v Speaker 2>A ninety seven. Their goal was a common protocol for

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<v Speaker 2>interoperability across the supply chain or really broad scope.

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<v Speaker 1>But before that it was more fragmented application specific standards mostly.

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<v Speaker 2>Yeah ANILID road tolls. Not much focus on broad tech

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<v Speaker 2>based standards covering different frequencies, so maybe ANSI. In the US.

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<v Speaker 2>A lot of early tech was proprietary, leading to closed systems,

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<v Speaker 2>and UHF had some regulatory issues too, potential overlap with

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<v Speaker 2>mobile phones in.

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<v Speaker 1>Some places, so a bit messy. Initially, it sounds like

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<v Speaker 1>RFID standards had some catching up to do compared to

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<v Speaker 1>say barcodes.

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<v Speaker 2>That's a key point from the sources. The barcode community

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<v Speaker 2>had a deep understanding of applications in tech when their

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<v Speaker 2>standards evolved. RFID was maybe ten twenty years behind in

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<v Speaker 2>that sense, starting almost from scratch in terms of consensus.

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<v Speaker 1>Must have been hard getting everyone on the same page

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<v Speaker 1>with all the different technologies.

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<v Speaker 2>Definitely, the first phase of ISO eighteen thousand tried to

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<v Speaker 2>set up rules, maybe one protocol pre frequency, but there

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<v Speaker 2>were just so many competing proprietary candidates.

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<v Speaker 1>What about the application side EPC Global had groups working

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<v Speaker 1>on that.

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<v Speaker 2>Yeah, those were crucial. They worked on things like lookup services, yeah,

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<v Speaker 2>the discovery service, supply chain tracking models, and importantly security

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<v Speaker 2>and privacy analysis, building prototypes.

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<v Speaker 1>So practical implementation, not just the tech specs right.

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<v Speaker 2>And business groups focused on sectors like anti counterfeiting, pharma, apparel, food,

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<v Speaker 2>running pilot projects to show the value any.

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<v Speaker 1>Cool examples of early smart object systems.

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<v Speaker 2>I mentioned smart shells for bookstores, remote servicing for heavy

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00:17:12.400 --> 00:17:17.160
<v Speaker 2>equipment using RFID to spot issues or manage parts, showing

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00:17:17.160 --> 00:17:19.319
<v Speaker 2>that potential beyond just tracking, and.

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00:17:19.200 --> 00:17:22.480
<v Speaker 1>The performance requirements for logistics were getting pretty demanding. Read

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<v Speaker 1>range speed.

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00:17:23.680 --> 00:17:26.359
<v Speaker 2>Yeah, reading up to nine meters, reading whole pallettes fast

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<v Speaker 2>like half a second to two seconds, needing new one

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<v Speaker 2>hundred percent accuracy which meant more power, higher data rates,

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<v Speaker 2>and people were already thinking about adding sensors.

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<v Speaker 1>To tag sensors like temperature shock.

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00:17:37.720 --> 00:17:42.319
<v Speaker 2>Exactly, temperature, humidity pressure. Moving beyond just ID to collecting

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<v Speaker 2>environmental data that needed more power and data capacity, of.

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<v Speaker 1>Course opens up a lot more possibilities. Okay, let's seme

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<v Speaker 1>in on the super small stuff ultra small RFID chips.

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<v Speaker 1>The hon chips, tiny chips and everyday objects. Sounds futuristic

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<v Speaker 1>even now.

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<v Speaker 2>It really does. The goal was linking physical things to

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00:18:00.640 --> 00:18:05.400
<v Speaker 2>network information. Small cheap chips for anti counterfeiting product tracking.

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<v Speaker 1>Like that chip at the IGXPO point four milimeter square Yeah, two.

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00:18:08.519 --> 00:18:10.440
<v Speaker 2>Point four or five getter herds one hundred and twenty

357
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<v Speaker 2>eight bit ID and the trend was even smaller like

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<v Speaker 2>Hatachi's sub point one millimeter chips.

359
00:18:16.079 --> 00:18:18.599
<v Speaker 1>Incredible like electronic dust. What's inside them.

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00:18:18.480 --> 00:18:20.839
<v Speaker 2>Basically ROM for the ID one twenty eight bits like

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00:18:20.880 --> 00:18:23.640
<v Speaker 2>an IPv six address conceptually, and a rectifier circuit to

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00:18:23.640 --> 00:18:26.839
<v Speaker 2>harvest RF energy for power. Early ones skipped anti collision

363
00:18:26.839 --> 00:18:27.720
<v Speaker 2>to save space.

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00:18:27.519 --> 00:18:28.079
<v Speaker 1>And the antenna.

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00:18:28.240 --> 00:18:29.920
<v Speaker 2>Some had it embedded right on the chip for two

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<v Speaker 2>point four or five gilaers, or you could attach an

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00:18:32.440 --> 00:18:35.240
<v Speaker 2>external one for longer range using special films, making thin,

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00:18:35.480 --> 00:18:38.400
<v Speaker 2>flexible tags possible. They're also working on batch assembly to.

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<v Speaker 1>Cut costs, miniaturization driving everything right. So digging into the

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<v Speaker 1>design of these passive tag ICs, what are the key

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<v Speaker 1>building blocks?

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<v Speaker 2>You need the rectifier obviously to get power, a voltage

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<v Speaker 2>regulator for stable supply, a demodulator to get data from

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<v Speaker 2>the reader, memory for the ID, a modulator to send

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<v Speaker 2>data back, usually.

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00:18:56.559 --> 00:18:59.400
<v Speaker 1>Backscatter where flex the reader signal.

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00:18:59.119 --> 00:19:02.319
<v Speaker 2>Right, it doesn't transmit its own and a clock generator

378
00:19:02.319 --> 00:19:03.319
<v Speaker 2>for timing the.

379
00:19:03.279 --> 00:19:07.119
<v Speaker 1>Recifier seems critical for passive tags. How did they optimize that?

380
00:19:07.599 --> 00:19:10.680
<v Speaker 2>They use things like the Dixon equation modified to account

381
00:19:10.720 --> 00:19:15.359
<v Speaker 2>for real world losses, capacitance, diode characteristics, load current frequency.

382
00:19:15.880 --> 00:19:18.680
<v Speaker 2>It's a complex balancing act choosing the right number of

383
00:19:18.720 --> 00:19:22.319
<v Speaker 2>stages matching the antenna impedance to grab as much power.

384
00:19:22.119 --> 00:19:25.200
<v Speaker 1>As possible, maximizing that energy scavenging. And once you have

385
00:19:25.240 --> 00:19:28.000
<v Speaker 1>the raw power, you need stable voltage exactly.

386
00:19:28.359 --> 00:19:31.240
<v Speaker 2>First, a DC limitter for basic protection against too much

387
00:19:31.319 --> 00:19:34.880
<v Speaker 2>voltage could be simple diodes or fancier transistor circuits for

388
00:19:34.960 --> 00:19:38.799
<v Speaker 2>tighter control, especially with low voltage processes. Then a fine

389
00:19:38.839 --> 00:19:42.000
<v Speaker 2>regulator for the precise voltage needed by the circuits.

390
00:19:41.640 --> 00:19:44.119
<v Speaker 1>And some tags needed to work at multiple frequencies.

391
00:19:44.359 --> 00:19:47.799
<v Speaker 2>Yeah, research into multi frequency rectifiers using coupling in switches

392
00:19:47.839 --> 00:19:51.559
<v Speaker 2>to handle LFHF and UAHF. Even the clock oscillator had

393
00:19:51.559 --> 00:19:54.640
<v Speaker 2>tight specs needed over one point nine middle hertz decent

394
00:19:54.720 --> 00:19:58.440
<v Speaker 2>voltage swing, but using incredibly low power like under five

395
00:19:58.480 --> 00:19:59.119
<v Speaker 2>hundred nano.

396
00:19:59.000 --> 00:20:02.920
<v Speaker 1>Wa amazing engineer ring in such tiny, simple looking tags. Okay,

397
00:20:03.000 --> 00:20:06.759
<v Speaker 1>last piece of the RFID puzzle. Printed electronics a totally

398
00:20:06.759 --> 00:20:09.000
<v Speaker 1>different way to make tags, potentially.

399
00:20:08.519 --> 00:20:12.400
<v Speaker 2>Game changing, using printing methods, often with organic materials, for

400
00:20:12.559 --> 00:20:16.880
<v Speaker 2>low cost, large area, high volume production. Think beyond RFID two,

401
00:20:16.880 --> 00:20:19.160
<v Speaker 2>smart packaging, flexible displays.

402
00:20:19.200 --> 00:20:21.480
<v Speaker 1>How does it work Layering materials.

403
00:20:20.960 --> 00:20:25.759
<v Speaker 2>Basically yeah, printing layers for substrate electrodes, semiconductor insulator building

404
00:20:25.920 --> 00:20:27.920
<v Speaker 2>devices like thin film transistors.

405
00:20:27.440 --> 00:20:31.119
<v Speaker 1>DFTs, so printing circuits instead of etching silicon. How did

406
00:20:31.160 --> 00:20:33.319
<v Speaker 1>printed transistors compared to siloton ones?

407
00:20:33.400 --> 00:20:37.759
<v Speaker 2>Qualitatively similar characteristics but generally much lower charge carrier mobility

408
00:20:37.799 --> 00:20:40.559
<v Speaker 2>so slower less current capacity and performance varies a lot

409
00:20:40.559 --> 00:20:41.960
<v Speaker 2>with materials and process but.

410
00:20:41.960 --> 00:20:43.559
<v Speaker 1>They could make working circuits.

411
00:20:43.839 --> 00:20:47.880
<v Speaker 2>Yeah, simple stuff like ring oscillators, even basic RFID transponders

412
00:20:47.920 --> 00:20:51.680
<v Speaker 2>with rectifier clock data circuits. It was early days, though,

413
00:20:52.119 --> 00:20:57.359
<v Speaker 2>Roadmaps highlighted printed rfid's potential, thin flexible, but also the limitations,

414
00:20:57.480 --> 00:21:02.519
<v Speaker 2>especially performance, kids were right memory in UHF operation. First

415
00:21:02.519 --> 00:21:05.000
<v Speaker 2>prototypes were being tested around two thousand and seven two.

416
00:21:04.839 --> 00:21:08.279
<v Speaker 1>Thousand and eight, so promising for ultra low cost flexible tags,

417
00:21:08.279 --> 00:21:11.279
<v Speaker 1>but still maturing, and finally, what about making these organic

418
00:21:11.319 --> 00:21:14.960
<v Speaker 1>tags compatible with EPC standards. That's crucial for supply chains.

419
00:21:14.759 --> 00:21:18.039
<v Speaker 2>Right, absolutely essential for organic tags to be widely adopted,

420
00:21:18.039 --> 00:21:21.599
<v Speaker 2>they need to play nice the existing EPC infrastructure. Plastic

421
00:21:21.599 --> 00:21:24.440
<v Speaker 2>tags already met some basic specs six four to ninety

422
00:21:24.480 --> 00:21:27.680
<v Speaker 2>six bit IDs HF operation, but work was on going

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00:21:27.720 --> 00:21:31.400
<v Speaker 2>to get higher data rates closer to full EPC compatibility.

424
00:21:30.839 --> 00:21:33.799
<v Speaker 1>Using new transistor tech like dual gate otfts.

425
00:21:33.920 --> 00:21:36.240
<v Speaker 2>Yeah, exploring things like that to boost performance, get better

426
00:21:36.240 --> 00:21:38.480
<v Speaker 2>gain and noise margines. In the logic, they showed a

427
00:21:38.480 --> 00:21:42.400
<v Speaker 2>fifty kilo ortz transponder using penasine for mobility special masking techniques.

428
00:21:42.680 --> 00:21:46.000
<v Speaker 2>Promising steps, but full EPC adherence for organic tags was

429
00:21:46.000 --> 00:21:47.200
<v Speaker 2>still a major research goal.

430
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<v Speaker 1>It's clear RFID was booming in twenty ten, Silicon chips, shrinking,

431
00:21:51.640 --> 00:21:55.640
<v Speaker 1>printed electronics emerging, all aimed at connecting the physical and

432
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<v Speaker 1>digital worlds.

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<v Speaker 2>And what's really interesting connecting it all back is how

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<v Speaker 2>these three air areas, Robust Design, Sigma, Delta, RFID were

435
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<v Speaker 2>all deeply tied to the underlying semiconductor progress. Nanoscale CMOS

436
00:22:08.559 --> 00:22:11.240
<v Speaker 2>was the engine driving opportunities but also creating challenges that

437
00:22:11.319 --> 00:22:16.079
<v Speaker 2>cut across all these fields. It pushed innovation everywhere materials, circuits,

438
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<v Speaker 2>design methods.

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<v Speaker 1>Okay, let's wrap up this steep dive. It's been quite

440
00:22:20.200 --> 00:22:23.559
<v Speaker 1>a journey through analog circuit design. Circuit twenty ten, we

441
00:22:23.599 --> 00:22:27.240
<v Speaker 1>saw the huge efforts in robust design handling extreme conditions,

442
00:22:27.319 --> 00:22:28.400
<v Speaker 1>nanoscale effects.

443
00:22:28.480 --> 00:22:31.119
<v Speaker 2>We looked at the clever innovations in Sigma delta converters,

444
00:22:31.279 --> 00:22:33.400
<v Speaker 2>pushing for better performance, lower.

445
00:22:33.160 --> 00:22:36.440
<v Speaker 1>Power, and we tracked the rise of RFID standardization, tiny

446
00:22:36.480 --> 00:22:39.519
<v Speaker 1>silicon ships, the potential of printed electronics, all heading towards

447
00:22:39.559 --> 00:22:40.359
<v Speaker 1>widespread use.

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00:22:40.559 --> 00:22:43.440
<v Speaker 2>For me, the aha moments, We're seeing how engineers were

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<v Speaker 2>getting smarter about managing variability and reliability at nanoscale, the

450
00:22:48.359 --> 00:22:52.680
<v Speaker 2>really inventive architectures in Sigma deltas, and just watching RFID

451
00:22:52.799 --> 00:22:57.039
<v Speaker 2>evolve from niche uses towards something potentially transformative, driven by

452
00:22:57.039 --> 00:22:58.799
<v Speaker 2>both silicon and new materials.

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<v Speaker 1>And hopefully for you listening, this gives you a solid

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<v Speaker 1>handle on these key trends and why they mattered without

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00:23:04.720 --> 00:23:07.480
<v Speaker 1>needing an engineering degree. We tried to hit the highlights

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<v Speaker 1>and the implications, which.

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<v Speaker 2>Leads to a final thought, maybe considering all this progress

458
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<v Speaker 2>back in twenty ten. How might these advancements, especially in

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00:23:15.400 --> 00:23:19.279
<v Speaker 2>robust electronics and pervasive tech like RFID, be shaping the

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00:23:19.319 --> 00:23:21.960
<v Speaker 2>devices we use now in how we interact with the world.

461
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<v Speaker 2>What entirely new applications might have popped up because these

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<v Speaker 2>technologies kept maturing and getting cheaper. Something to think about.
